Many modern electronic systems involve analog-to-digital converters (ADCs) and/or digital-to-analog converters (DACs). One example ADC topology is referred to as top plate sampling ADC topology. In a top plate sampling ADC topology, an input signal is sampled using a capacitor having a first node coupled to a sampling switch and a second node coupled to ground. In a top plate sampling ADC topology, the front-end circuitry (e.g., a flash stage) receives a full input and provides a multi-bit output that is fed to a multi-bit DAC. The analog output of the DAC is subtracted from the ADC input, and the “residue” of the subtraction is then gained up and is fed to the next stage.
One technique to gain up the residue involves a dynamic integrator. As bandwidths and speeds of ADC operations increase, the time available for integration decreases, which results in increased power consumption to achieve a target gain. Also, a sampling switch at the output of a dynamic integrator presents an additional load that degrades integrator performance.